1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device provided with a circuit carrying out a test for reliability evaluation.
2. Description of the Background Art
Generally, periods in which failures occur in a device such as a semiconductor memory device are roughly divided into three periods over time: an initial failure period, a chance failure period, and a wear-out failure period. An initial failure occurs immediately after starting the use of the device, which is attributable to a defect during manufacture of the device. For example, an insufficient margin belongs to this type. The rate of the initial failure decreases sharply with the passage of time. The initial failure period is followed by the chance failure period where a low failure rate continues for a certain long period of time. Near the end of useful life, the device enters the wear-out failure period where the failure rate suddenly increases. It is desirable that a device is used within the chance failure period which corresponds to the useful life period. In order to increase reliability of a device, the chance failure period should last for a long period of time with a constant, low failure rate.
On the other hand, in order to eliminate the initial failure in advance, there is a need to perform accelerated operation aging on devices for a certain period of time, for screening to reject defective products. Such screening will be performed effectively within a short period of time if the initial failure rate decreases rapidly to make the device promptly enter the chance failure period. One of such screening methods generally employed at present is a high-temperature operation test (burn-in test), which employs real devices to directly evaluate dielectric films of transistors and others. With this method, stress of high temperature and high field is applied, so that every cause of failure including short circuit between interconnections can be elicited with accelerated speed.
In the burn-in test, however, stress of high field, i.e., a high voltage should be applied to devices, resulting in power consumption of a considerable amount during the test. In this regard, Japanese Patent Laying-Open No. 2000-173296, for example, discloses a method for decreasing power consumption during the burn-in test by making its inspection step short.
Such a method, however, requires special devices or complicated control for shortening the inspection step.
Moreover, in accordance with a recent demand for devices of higher speed and lower voltage, a transistor having a low threshold voltage (hereinafter, also referred to as the “Low-Vth transistor”) has generally been used as a circuit element. Such a Low-Vth transistor suffers a leakage current when turned off, due to its low threshold voltage. In particular, the leakage current would further increase when stress of high field is applied as in the case of the above-described burn-in test, than in a normal operation.